Module VDCTRL0_CLR

LCDIF VSYNC Mode and Dotclk Mode Control Register0

Modules

• DOTCLK_POL
  Default is data launched at negative edge of DOTCLK and captured at positive edge
• ENABLE_POL
  Default 0 active low during valid data transfer on each horizontal line.
• ENABLE_PRESENT
  Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK
• HALF_LINE
  Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i
• HALF_LINE_MODE
  When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line
• HSYNC_POL
  Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period
• VSYNC_PERIOD_UNIT
  Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles
• VSYNC_POL
  Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period
• VSYNC_PULSE_WIDTH
  Number of units for which VSYNC signal is active
• VSYNC_PULSE_WIDTH_UNIT
  Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles