Expand description
LCDIF VSYNC Mode and Dotclk Mode Control Register2
Modulesยง
- HSYNC_
PERIOD - Total number of DISPLAY CLOCK (pix_clk) cycles between two positive or two negative edges of the HSYNC signal
- HSYNC_
PULSE_ WIDTH - Number of DISPLAY CLOCK (pix_clk) cycles for which HSYNC signal is active.