Module imxrt_ral::lcdif::VDCTRL3

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LCDIF VSYNC Mode and Dotclk Mode Control Register3

Modules§

  • HORIZONTAL_WAIT_CNT
    In the DOTCLK mode, wait for this number of clocks from falling edge (or rising if HSYNC_POL is 1) of HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving picture information begins
  • MUX_SYNC_SIGNALS
    When this bit is set, the LCDIF block will internally mux HSYNC with LCD_D14, DOTCLK with LCD_D13 and ENABLE with LCD_D12, otherwise these signals will go out on separate pins
  • VERTICAL_WAIT_CNT
    In the VSYNC interface mode, wait for this number of DISPLAY CLOCK (pix_clk) cycles from the falling VSYNC edge (or rising if VSYNC_POL is 1) before starting LCD transactions and is applicable only if WAIT_FOR_VSYNC_EDGE is set
  • VSYNC_ONLY
    This bit must be set to 1 in the VSYNC mode of operation, and 0 in the DOTCLK mode of operation.