Struct imxrt_ral::lpi2c::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 28 fields
    pub VERID: RORegister<u32>,
    pub PARAM: RORegister<u32>,
    pub MCR: RWRegister<u32>,
    pub MSR: RWRegister<u32>,
    pub MIER: RWRegister<u32>,
    pub MDER: RWRegister<u32>,
    pub MCFGR0: RWRegister<u32>,
    pub MCFGR1: RWRegister<u32>,
    pub MCFGR2: RWRegister<u32>,
    pub MCFGR3: RWRegister<u32>,
    pub MDMR: RWRegister<u32>,
    pub MCCR0: RWRegister<u32>,
    pub MCCR1: RWRegister<u32>,
    pub MFCR: RWRegister<u32>,
    pub MFSR: RORegister<u32>,
    pub MTDR: WORegister<u32>,
    pub MRDR: RORegister<u32>,
    pub SCR: RWRegister<u32>,
    pub SSR: RWRegister<u32>,
    pub SIER: RWRegister<u32>,
    pub SDER: RWRegister<u32>,
    pub SCFGR1: RWRegister<u32>,
    pub SCFGR2: RWRegister<u32>,
    pub SAMR: RWRegister<u32>,
    pub SASR: RORegister<u32>,
    pub STAR: RWRegister<u32>,
    pub STDR: WORegister<u32>,
    pub SRDR: RORegister<u32>,
    /* private fields */

}
Expand description

LPI2C

Fields§

§VERID: RORegister<u32>

Version ID Register

§PARAM: RORegister<u32>

Parameter Register

§MCR: RWRegister<u32>

Master Control Register

§MSR: RWRegister<u32>

Master Status Register

§MIER: RWRegister<u32>

Master Interrupt Enable Register

§MDER: RWRegister<u32>

Master DMA Enable Register

§MCFGR0: RWRegister<u32>

Master Configuration Register 0

§MCFGR1: RWRegister<u32>

Master Configuration Register 1

§MCFGR2: RWRegister<u32>

Master Configuration Register 2

§MCFGR3: RWRegister<u32>

Master Configuration Register 3

§MDMR: RWRegister<u32>

Master Data Match Register

§MCCR0: RWRegister<u32>

Master Clock Configuration Register 0

§MCCR1: RWRegister<u32>

Master Clock Configuration Register 1

§MFCR: RWRegister<u32>

Master FIFO Control Register

§MFSR: RORegister<u32>

Master FIFO Status Register

§MTDR: WORegister<u32>

Master Transmit Data Register

§MRDR: RORegister<u32>

Master Receive Data Register

§SCR: RWRegister<u32>

Slave Control Register

§SSR: RWRegister<u32>

Slave Status Register

§SIER: RWRegister<u32>

Slave Interrupt Enable Register

§SDER: RWRegister<u32>

Slave DMA Enable Register

§SCFGR1: RWRegister<u32>

Slave Configuration Register 1

§SCFGR2: RWRegister<u32>

Slave Configuration Register 2

§SAMR: RWRegister<u32>

Slave Address Match Register

§SASR: RORegister<u32>

Slave Address Status Register

§STAR: RWRegister<u32>

Slave Transmit ACK Register

§STDR: WORegister<u32>

Slave Transmit Data Register

§SRDR: RORegister<u32>

Slave Receive Data Register

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