Module MISC2_CLR

Miscellaneous Control Register

Modules

• AUDIO_DIV_LSB
  LSB of Post-divider for Audio PLL
• AUDIO_DIV_MSB
  MSB of Post-divider for Audio PLL
• PLL3_DISABLE
  Default value of “0”
• REG0_BO_OFFSET
  This field defines the brown out voltage offset for the CORE power domain
• REG0_BO_STATUS
  Reg0 brownout status bit.
• REG0_ENABLE_BO
  Enables the brownout detection.
• REG0_STEP_TIME
  Number of clock periods (24MHz clock).
• REG1_BO_OFFSET
  This field defines the brown out voltage offset for the xPU power domain
• REG1_BO_STATUS
  Reg1 brownout status bit.
• REG1_ENABLE_BO
  Enables the brownout detection.
• REG1_STEP_TIME
  Number of clock periods (24MHz clock).
• REG2_BO_OFFSET
  This field defines the brown out voltage offset for the xPU power domain
• REG2_BO_STATUS
  Reg2 brownout status bit.
• REG2_ENABLE_BO
  Enables the brownout detection.
• REG2_OK
  Signals that the voltage is above the brownout level for the SOC supply
• REG2_STEP_TIME
  Number of clock periods (24MHz clock).
• VIDEO_DIV
  Post-divider for video