imxrt_ral
0.6.0
In imxrt_ral::semc::MCR::DQSSEL::RW
Constant
imxrt_ral
::
semc
::
MCR
::
DQSSEL
::
RW
::
DQSSEL_0
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source
ยท
[
−
]
pub const DQSSEL_0:
u32
= 0;
Expand description
SDRAM/NOR/SRAM read clock source is from DQS pad in synchronous mode.