Module RW

Source

Constantsยง

OUTMODE_0
Asserted while counter is active
OUTMODE_1
Clear OFLAG output on successful compare
OUTMODE_2
Set OFLAG output on successful compare
OUTMODE_3
Toggle OFLAG output on successful compare
OUTMODE_4
Toggle OFLAG output using alternating compare registers
OUTMODE_5
Set on compare, cleared on secondary source input edge
OUTMODE_6
Set on compare, cleared on counter rollover
OUTMODE_7
Enable gated clock output while counter is active