imxrt_ral::usbphy

Module DEBUG_CLR

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Expand description

USB PHY Debug Register

Modulesยง

  • Gate Test Clocks
  • Use holding registers to assist in timing for external UTMI interface.
  • Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown
  • Set bit to allow squelch to reset high-speed receive.
  • Set this bit to allow a countdown to transition in between TX and RX.
  • Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.
  • Set bit 3 to 1 to pull down 15-KOhm on USB_DP line
  • Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value
  • Delay in between the detection of squelch to the reset of high-speed RX.
  • Duration of RESET in terms of the number of 480-MHz cycles.
  • Delay in between the end of transmit to the beginning of receive