Module CTRL1

Control 1 Register

Modules

• BOFFMSK
  This bit provides a mask for the Bus Off Interrupt.
• BOFFREC
  This bit defines how FLEXCAN recovers from Bus Off state
• ERRMSK
  This bit provides a mask for the Error Interrupt.
• LBUF
  This bit defines the ordering mechanism for Message Buffer transmission
• LOM
  This bit configures FLEXCAN to operate in Listen Only Mode
• LPB
  This bit configures FlexCAN to operate in Loop-Back Mode
• PRESDIV
  This 8-bit field defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency
• PROPSEG
  This 3-bit field defines the length of the Propagation Segment in the bit time
• PSEG1
  This 3-bit field defines the length of Phase Buffer Segment 1 in the bit time
• PSEG2
  This 3-bit field defines the length of Phase Buffer Segment 2 in the bit time
• RJW
  This 2-bit field defines the maximum number of time quanta One time quantum is equal to the Sclock period
• RWRNMSK
  This bit provides a mask for the Rx Warning Interrupt associated with the RWRN_INT flag in the Error and Status Register
• SMP
  This bit defines the sampling mode of CAN bits at the FLEXCAN_RX
• TSYN
  This bit enables a mechanism that resets the free-running timer each time a message is received in Message Buffer 0
• TWRNMSK
  This bit provides a mask for the Tx Warning Interrupt associated with the TWRN_INT flag in the Error and Status Register