Module PLL_USB2

Source
Expand description

Analog USB2 480MHz PLL Control Register

Modulesยง

BYPASS
Bypass the PLL.
BYPASS_CLK_SRC
Determines the bypass source.
DIV_SELECT
This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.
ENABLE
Enable the PLL clock output.
EN_USB_CLKS
0: 8-phase PLL outputs for USBPHY1 are powered down
LOCK
1 - PLL is currently locked. 0 - PLL is not currently locked.
POWER
Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens.