Module VDCTRL4

LCDIF VSYNC Mode and Dotclk Mode Control Register4

Modules

DOTCLK_DLY_SEL

This bitfield selects the amount of time by which the DOTCLK signal should be delayed before coming out of the LCD_DOTCK pin

DOTCLK_H_VALID_DATA_CNT

Total number of DISPLAY CLOCK (pix_clk) cycles on each horizontal line that carry valid data in DOTCLK mode

SYNC_SIGNALS_ON

Set this field to 1 if the LCD controller requires that the VSYNC or VSYNC/HSYNC/DOTCLK control signals should be active at least one frame before the data transfers actually start and remain active at least one frame after the data transfers end